1. Field of the Invention
The present invention relates to a structure of a semiconductor device and more particularly to an outer peripheral structure of a power control semiconductor device.
2. Description of the Background Art
A power control semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) has been widely used for commercial-off-the-shelf equipment to electric railroad purposes. While the IGBT has been developed to minimize its loss, withstanding capability expressed by use of a SOA (Safe Operating Area) as an indicator is lowered, in general. The SOA includes a RBSOA (Reverse Bias SOA). The RBSOA is the SOA when a reverse bias is applied to the IGBT, and it is an indicator of withstanding capability at the time of a turn-off operation. A technique to prevent the withstanding capability from being lowered has been required.
Meanwhile, Japanese Patent Application Laid-Open No. 4-162777 (1992) (FIGS. 1 and 5) discloses a configuration in which a planar guard ring having a mesa structure on its lower surface side is provided on an upper surface side of an outer peripheral part, and a glass film is provided on a bevel surface of the mesa structure as a protection film, in a reverse blocking thyristor. This configuration is made to solve a problem in double-sided planar structure that causes discharge between an end face of a silicon substrate and a substrate (support substrate) to support the silicon substrate with an electrode interposed therebetween, and a problem in double-sided mesa structure that lowers strength of a wafer.
A conventional IGBT has a laminated structure including a lifetime killer layer, an n type buffer layer, and a p type collector layer each having uniform impurity concentration provided under an n− type drift layer, on its lower surface side (collector side) including a cell region and a guard ring region provided on the outer side thereof. Thus, when the IGBT is turned on, holes are injected from the p type collector layer on the lower surface side into the n− type drift layer in the guard ring region as well as in the cell region.
Meanwhile, electrons are injected from an upper surface (emitter side) of the IGBT only from a MOSFET part in the cell region of the IGBT to the n− type drift layer, so that they are not injected from an upper surface in the guard ring region. Therefore, when the IGBT is in on state, holes and electrons are held in equilibrium in the n− type drift layer in the cell region and conductivity modulation is generated, but the holes remain in the n− type drift layer in the guard ring region.
When the IGBT is turned off after the on state, the electron injection from the upper surface side is stopped, the holes remaining in the n− type drift layer near the n type buffer layer are trapped by the lifetime killer layer, and the ones close to the upper surface is absorbed into a p type well (base region) having an emitter of the IGBT, and the rest disappear by its natural lifetime. Here, since the emitter is not provided on the upper surface side of the guard ring region, the holes provided close to the upper surface of the guard ring region try to intensively flow into the p type well of the IGBT cell provided in an outermost periphery in the cell region. At this time, when an amount of the holes absorbed into the p type well provided in the outermost periphery of the IGBT cell exceeds a certain value, thermal destruction is caused at that part, which lowers cutoff destruction withstand capability of the IGBT.
In addition, since the thyristor disclosed in the patent document 1 has a large effective area in a cell, there is no problem of the thermal destruction caused by current concentrated in an outer peripheral part of the cell.
Meanwhile, a PiN (p-intrinsic-n) diode having a cathode on the lower surface side of a substrate has the same problem as that of the IGBT. That is, when the diode is on state, holes are injected from a p type anode region on the upper surface side of a cell region and electrons are injected from an n type cathode layer on the lower surface side, into an n− type drift layer. At this time, electrons are injected from the n type cathode layer in the guard ring region similar to the cell region, so that a considerable amount of holes flows into the n− type drift layer in the guard ring region, from the cell region.
When the diode is turned off, the electrons stored in the n− type drift layer in the on state are discharged to the n type cathode layer, and the holes are discharged to the p type anode region. In addition, the electrons and holes are partially recombined and disappear. At this time, the holes stored in the n− type drift layer in the guard ring region try to intensively flow into the p type anode region provided in an outermost periphery in the cell region. As a result, reverse recovery current is concentrated in the outer peripheral part of the cell region, so that reverse recovery withstand capability is lowered in the diode.
In addition, since electric field intensity is concentrated in an upper surface of a substrate in a conventional guard ring structure (FLR: Field Limiting Ring), it is necessary to increase a width of a guard ring to prevent the electric field from being concentrated. However, the width of the outer peripheral structure is preferably small with a view to miniaturizing a device.